Description.

In this project, we will use semiconductor device simulation software (Synopsys’ Sentaurus TCAD) to design an N-channel Si MOSFET with gate length, LG = 25 nm (relevant for the “20 nm generation” of CMOS technology) to meet specified performance requirements within some practical design constraints. The simulator represents the transistor structure as a mesh of points, keeping track of the material properties and net dopant concentration (within a semiconductor material) at each point and self-consistently solving the Poisson equation and continuity equations to find the mobile charge carrier (electron and hole) concentrations, electric field, electric potential, and current flow at each point.

Analytical models are used to calculate the effective mass and carrier mobilities and to account for phenomena such as band gap narrowing, generation-recombination, band-to-band (Zener) tunneling, and velocity saturation. For a specified transistor structure and operating conditions (e.g., bias voltages and temperature), terminal currents can be derived. If the transistor structure were described in two dimensions (as is the case for this project), then, the simulator would assume that the transistor width (i.e., the MOSFET channel width) is 1 μm.

NMOS Design.

Final Design Parameters and Performance Specifications:

• Channel/Body Doping: 3E+18

• Junction Depth: 10 nm

• Spacer Length: 20 nm

• Active Current: 400.6 μA

• Leakage Current: 0.157 nA

• On/Off Ratio: 2.545E+6

Device Visualization (plot generated by Sentaurus Workbench):

Design Process.

Without modifications, the default parameter set was simulated (Lsp = 20nm, Doping = 1×10^17 cm-3, Xj = 13nm) and generated Ion = 1312 μA and Ioff = 102.9 μA with relatively low current ratio of 12.75. It is noticeable that Ioff = 102.9 μA is too high comparing to our desired specifications while Ion = 1312 μA doesn’t leave us orders of magnitude headroom to work with. Therefore, our main design goal is to minimize Ioff without sacrificing Ion too much.

Since increasing doping, shortening Xj, and enlarging Lsp will all reduce Ioff (desired) and Ion (undesired) at the same time, investigation of how each design parameter affect Ion and Ioff differently is needed first to provide insights for the optimization process later on.

Keeping Xj =13nm and Lsp = 20nm constant, the device was simulated with different doping concentrations to explore how doping affect Ion and Ioff differently.

Clearly, we can see that saturation current changes with doping concentration linearly while leakage current changes with doping exponentially. As a result, the On/Off current ratio also increases almost exponentially.

According to the simulation data above, it is desirable to further optimize the doping concentration as increasing it significantly lowers the leakage current without sacrificing too much saturation current. Moreover, doping can be more accurately and efficiently controlled in today’s fabrication process comparing to other parameters. Therefore, without changing other parameters, the doping concentration is pushed to the maximum (NA = 4E+18, Xj = 13nm, Lsp = 20nm), an saturation current of 492 µA and a leakage current of 1.782 nA is found. Comparing to the default value, the leakage current is greatly improved, however, it still can’t meet the performance specification. Thus, it’s impossible to simply optimize one parameter to achieve our design goal, Xj and Lsp also need to be co-optimized.

Experimenting similarly with Xj and Lsp, it becomes clear that Xj has more significant impact on the leakage current (smaller Xj helps to reduce leakage current, however it will result in a larger Source/Drain series resistance value to degrade saturation current) and Lsp has a “sweet spot” around 20-24 nm (increasing Lsp from 10 nm to 20 nm greatly reduces the leakage current while saturation current decays almost linearly, however, after 24nm both currents decrease linearly), so Xj is co-optimized with NA to achieve the design goal while Lsp is remained around 20-24 nm.

Finally, after over 20 groups of simulations, a few candidate parameter sets that meet the performance specifications are found. Among them, the parameter set of Lsp = 20 nm, Doping = 3E+18 cm-3, Xj = 10 nm has the highest On/Off current ratio of about 2.545E+6 , which is about 200,000 times better than that of the default parameter set.

Performance Specifications.

• Subthreshold Swing: 95.75 mV/dec

• Linear Threshold Voltage: 0.555 V

• Saturation Threshold Voltage: 0.440 V

• Drain-Induced Barrier Lowering: 153 mV/V

Reflections.

Dispersion between Simulated Value and Calculated Value:

The difference may be caused by the following reasons:

• In the MOSCAP theory, we assumed that oxide has zero charge, no current can pass through it, and gate charge is purely balanced by inversion charge. However, for actual (simulated) device, these assumptions are no longer true as the oxide and interfaces may also obtain certain non-idealities such as non-zero charge, tunneling current, and unbalanced gate charge.

• In the MOSCAP theory, we also assumed that the substrate beneath the gate area is a uniformly doped silicon body. However, as we can see from the actual device structure, the source/drain extension regions may extend to the area under the gate and further reduce channel length. This device feature alternates the doping profile and make many default assumptions in the MOSCAP theory invalid.

• More importantly, VT decreases with decreasing LG. Comparing to long-channel device with similar device parameters, our short-channel device would have a lower energy barrier and thus lower threshold voltage.

In conclusion, the expressions we derived in the MOSCAP chapter are quite simplified and may only suit well for ideal long-channel devices. Short-channel effects (VT Roll-off, Velocity Saturation, S/D Series Resistance, Surface Scattering, etc.) will have significant impacts on the device characteristics and idealities, resultantly changing VT from MOSCAP theory’s prediction.

Square-law Dependence:

Even though the square law dependency appears to be a better fit, the Velocity Saturation effect is more prominent and thus cannot be neglected. As a short-channel device, the designed device exhibits a linear dependence of Saturation Current on VGS due to Velocity Saturation instead of a quadratic dependence despite that square-law model appears to fit better at first glance.

Effective Oxide Thickness:

For future device with further reduced gate length, the oxide thickness needs to be further reduced accordingly to control VT roll-off, reduce Subthreshold Swing, and provide larger Cox to raise Ion. However, if the oxide layer is too thin, the tunneling leakage current would become significant and the device would become easier to breakdown due to high electric field. As a result, the limitations of oxide layer thickness reversely limit further shrinkage of gate length. Therefore, High-K oxide materials and new device structures are needed to overcome the oxide thickness limitations for future generations of devices when gate length is further reduced.

Due to Academic Integrity compliance requirements, please contact me for the full report.