Background.

Since the 70s, the integrated circuits shrink at an exponential speed from the scale of micrometers down to even a few nanometers.

But why are we doing that? Well, there are mainly 4 benefits of downscaling IC:

• Firstly, Due to the more compact device dimensions, lower supply voltages are needed to drive the device, reducing both leakage and dynamic power consumption.

• Secondly, it lowers production cost because the smaller the package gets, the more units can be lithographed on the silicon wafer, exponentially reducing manufacturing costs per unit.

• Thirdly, smaller device is faster to switch and operate, enabling higher clock speed. The component density also increases thus more computing power can be stacked on the same area.

• Finally, smaller and more power efficient IC enables many new fields of applications such as wearable devices and internet of things.

However, shrinking capacitors, one of the most important passive devices that is widely used as signal filters and storage cells, is quite challenging in the industry. Most of the on-board capacitors we previously used are either Electrolytic or Ceramic Capacitors made of metals or metal Electrolyte as the electrodes and metal oxide, or ceramic as the dielectric, with a size over few millimeters. In order to scale down to the nanoscale, MIM capacitors are introduced in the industry and are widely used as DRAM units in today’s IC packages.  

Current Solution.

To fulfill the desired material and structure properties mentioned in the previous slide, most of the commercially available MIM capacitors in today are made with Zirconium dioxide-based Aluminum oxide as the high-k dielectric film, also known as the ZAZ structure.

However, this structure has a few disadvantages:

1. The relatively low permittivity of Al2O3 (k=6) and ZrO2 (k=20~40) result in high capacitance equivalent thickness (CET) of the overall dielectric stack, preventing further shrinkage of the device without performance degradation.

2. Thickness scaling of the ZAZ becomes challenging as the ZrO2 crystallization is reduced by the Al2O3 interfacial layer.

3. The lattice mismatches between ZrO2 (a = 5.27 Å), Al2O3 (a = 4.79 Å), and TiN (a = 4.24 Å) substrate are relatively high, preventing growth of defect-free epitaxial film when further downscale.

Our Proposal.

Thus, in order to amend the disadvantages of the ZAZ form while inspired by it, we proposed the following new solution, an STO based Strontium oxide layer with Strontium ruthenate trioxide as the base electrode, which has the following advantages comparing to the ZAZ form:

1. Higher permittivity than Al2O3 and ZrO2, resulting in much lower capacitance equivalent thickness of the dielectric stack, allowing further downscaling or performance improvement at the same scale.

2. The SrRuO3 substrate allows better leakage current control comparing to TiN or SiO substrates.

3. The lattice mismatches at interfaces are significantly reduced as their lattice constants get closer, enabling growth of defect-free epitaxial film.